View MC3336406_754282.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC33364 Critical Conduction GreenLinet SMPS Controller
The MC33364 series are variable frequency SMPS controllers that operate in the critical conduction mode. They are optimized for high density power supplies requiring minimum board area, reduced component count, and low power dissipation. Integration of the high voltage startup saves approximately 0.7 W of power compared to the value of the resistor bootstrapped circuits. Each MC33364 features an on-board reference, UVLO function, a watchdog timer to initiate output switching, a zero current detector to ensure critical conduction operation, a current sensing comparator, leading edge blanking, a CMOS driver and cycle-by-cycle current limiting. The MC33364D1 has an internal 126 kHz frequency clamp. The MC33364D2 is available without an internal frequency clamp. The MC33364D has an internal 126 kHz frequency clamp which is pinned out, so that the designer can adjust the clamp frequency by connecting appropriate values of resistance.
Features http://onsemi.com MARKING DIAGRAMS
8 8 1 SO-8 D1, D2 SUFFIX CASE 751 1 M64Dx ALYW G
16 SO-16 D SUFFIX CASE 751K 1 1 MC33364D AWLYWWG
* * * * * * * *
16
Lossless Off-Line Startup Leading Edge Blanking for Noise Immunity Watchdog Timer to Initiate Switching Operating Temperature Range -25 to +125C Shutdown Capability Over Temperature Protection Optional/Adjustable Frequency Clamp to Limit EMI Pb-Free Packages are Available
x A WL Y W, WW G G
= = = = = = =
1 or 2 Assembly Location Wafer Lot Year Work Week Pb-Free Package Pb-Free Package
ORDERING INFORMATION
Device MC33364D1 MC33364D1G MC33364D1R2 MC33364D1R2G MC33364D2 MC33364D2G MC33364D2R2 MC33364D2R2G MC33364D MC33364DG MC33364DR2 MC33364DR2G Package SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) SO-16 SO-16 (Pb-Free) SO-16 SO-16 (Pb-Free) 2500 Units / Tape & Reel 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail Shipping
PIN CONNECTIONS
MC33364D1 MC33364D2 Zero Current Current Sense Voltage FB Vref 1 2 3 4 (Top View) MC33364D Zero Current N/C Current Sense Voltage FB N/C Vref N/C Freq Clamp 1 2 3 4 5 6 7 8 (Top View) 13 N/C 12 Vcc 11 Gate Drive 10 P GND 9 A GND 16 Line 8 Line 7 VCC 6 Gate Drive 5 GND
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
1
July, 2006 - Rev. 16
Publication Order Number: MC33364/D
MC33364
Vref Vcc Line Startup Vref + - turn on UVLO + - 15V/ 7.6V UVLO Thermal Shutdown 45k FB 15k Watchdog Timer Vcc R - + 0.1V FC Frequency Clamp R S Q Level SNA Gate P Gnd A Gnd + - Reset 15V/ var Vcc
Vref regulator turn on UVLO
15V/ 8.1V ZCD Vref 10V 5k 1.2V/ 1.0V - +
CS
LEB
Figure 1. Representative Block Diagram
Input AC Voltage
Output Voltage
MC33364D ZCD Line CS FB Rsense Vref FC
Vcc Drive P Gnd A Gnd
R1
R2
Figure 2. Typical Application Circuit
http://onsemi.com
2
MC33364
Startup circuit is charging the VCC capacitor 15V Supply Voltage, VCC Startup circuit turns off when VCC is 15V
8.1V VT (3.5 to 6V) 5V Startup circuit turns on when VCC reaches the threshold VT Reference Voltage, Vref
0V Vref regulator turns on when VCC reaches 15V Vref regulator turns off when VCC falls below 8.1 V Vref falls faster than VCC since Vref capacitor is much smaller than VCC capacitor
Maximum drain current is limited to 1.15V / Rsense
Drain Current 0A Switching starts when Vref reaches 5V Switching stops when Vref falls below 3.7V
Figure 3. Timing Diagram in Fault Condition
Criticial Mode Output Current Maximum drain current is limited to 1.15V/ Rsense Drain Current LEB Discontinous Conduction Mode No load
toff(min) Secondary Side Diode Current
Vin Drain Voltage
10V Voltage at ZCD 0.7V ZCD is ignored during minimum off-time limit
Figure 4. Timing Diagram in Normal Condition http://onsemi.com
3
MC33364
PIN DESCRIPTION
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAA AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A
AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A
1 (1) Zero Current Detect The ZCD Pin ensures critical conduction mode. ZCD monitors the voltage on the auxiliary winding, during the demagnetization phase of the transformer, comparing it to an internal reference. The ZCD sets the latch for the output driver. The Current Sense Pin monitors the current in the power switch by measuring the voltage across a resistor. Leading Edge Blanking is utilized to prevent false triggering. The voltage is compared to a resistor divider connected to the Voltage Feedback Pin. A 110 mV voltage off-set is applied to compensate the natural optocoupler saturation voltage. The Voltage Feedback Pin is typically connected to the collector of the optocoupler for feedback from the isolated secondary output. The Feedback is connected to the Vref Pin via a 5 k resistor providing bias for the external optocoupler. The Vref Pin is a buffered internal 5.0 V reference with Undervoltage Lockout. 3 (2) Current Sense 4 (3) Voltage Feedback 6 (4) Vref 8 (NA) Frequency Clamp The Frequency Clamp Pin ensures a minimum off-time value, typically 6.9 ms. It prevents the MOSFET from restarting within a fixed (33364D1) or adjustable (33364D) delay. The minimum off-time is disabled in the 33364D2. Therefore the maximum switching frequency cannot exceed 1/(TON + TOFFmin). This pin is the ground for the internal circuitry excluding the gate drive stage. This pin is the ground for the gate drive stage. 9 (5) A GND P GND 10 (5) 11 (6) Gate Drive VCC The gate drive is the output to drive the gate of the power MOSFET. 12 (7) 16 (8) Provides the voltage for all internal circuitry including the gate drive stage and Vref. This pin has Undervoltage Lockout with hysteresis. The Line Pin provides the initial power to the VCC pins. Internally the line pin is a high voltage current source, eliminating the need for an external startup network. Line NOTE: For further information please refer to the following Application Notes; AN1594: Critical Conduction Mode, Flyback Switching Power Supply Using the MC33364. AN1681: How to keep a Flyback Switch-Mode Power Supply Stable with a Critical-Mode Controller.
Pin
Function
Description
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Rating Symbol VCC Value 16 Unit V V V Power Supply Voltage (Operating) Line Voltage
VLine Vin1 Iin Iin
700
Current Sense, Compensation, Voltage Feedback, Restart Delay and Zero Current Input Voltage Zero Current Detect Input Restart Diode Current
-1.0 to +10 5.0 5.0
mA mA
Power Dissipation and Thermal Characteristics D1 and D2 Suffix, Plastic Package Case 751 Maximum Power Dissipation @ TA = 70C Thermal Resistance, Junction-to-Air D Suffix, Plastic Package Case 751B-05 Maximum Power Dissipation @ TA = 70C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range
PD RqJA PD RqJA TJ
450 178 550 145 150
mW C/W mW C/W C C C
TA
-25 to +125 -55 to +150
Tstg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: ESD data available upon request.
http://onsemi.com
4
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A
TOTAL DEVICE FREQUENCY CLAMP UNDERVOLTAGE LOCKOUT TIMER THERMAL SHUTDOWN LEADING EDGE BLANKING DRIVE OUTPUT CURRENT SENSE COMPARATOR ZERO CURRENT DETECTOR VCC Off State Consumption (VCC = 11 V) VCC Dynamic Operating Current (50 kHz, CL = 1.0 nF) Line Startup Current (VCC = 0 V, VLine = 50 V) Line Pin Leakage (VLine = 500 V) Line Startup Current (VLine = 50 V) (VCC = Vth(on) - 1.0 V) Restart Delay Time Dead Time (FC pin = 1.7 V) Frequency Clamp Control Current Range (Sink) Frequency Clamp Input Threshold Internal FC Function (pin grounded) Internal FC Function (pin open) Minimum Operating Voltage After Turn-On (VCC Decreasing) Startup Threshold (VCC Increasing) Watchdog Timer Shutdown (Junction Temperature Increasing) Hysteresis (Junction Temperature Decreasing) Delay to Current Sense Comparator Input (VFB = 2.0 V, VCS = 0 V to 4.0 V step, CL = 1.0 nF) Output Voltage in Undervoltage (VCC = 7.0 V, ISink = 1.0 mA) Output Voltage Fall Time (75% - 25%) (CL = 1.0 nF) Output Voltage Rise Time (25% - 75%) (CL = 1.0 nF) Source Resistance (Drive = 0 V, VGate = VCC - 1.0 V) Sink Resistance (Drive = VCC, VGate = 1.0 V) Feedback Pin to Output Delay Feedback Pin Input Range Built In Offset Input Bias Current (VCS = 0 to 2.0 V) Input Clamp Voltage - High State (IDET = 3.0 mA) Input Clamp Voltage - Low State (IDET = -3.0 mA) Hysteresis (Vin Decreasing) Input Threshold Voltage (Vin Decreasing) tPHL(in/out) VShutdown Vth(FC) VO(UV) IControl Vth(on) ICC Off ROH ROL ILine ILine ILine tDLY fmax fmax tDLY tDLY VFB VIO VIH VIL ICC Tsd TH Vth VH Td IIB tr tf 1.89 -0.5 9.0 -1.1 300 400 104 200 100 1.5 6.0 0.5 5.0 3.5 6.5 1.1 0.9 30 14 10 5 50 - - - - - - - 10.33 -0.75 2.75 1.95 0.01 1.24 0.02 544 8.5 100 564 126 360 180 50 250 232 108 200 5.0 7.6 1.0 10 32 70 15 28 67 36 11 2.01 0.03 800 800 145 700 150 400 170 110 4.5 6.5 8.5 1.4 0.5 12 0.5 1.1 12 70 12 16 50 70 25 - - - - kHz kHz mA mA mA ms mV mV mA mA mA mA C ns ns ns ns ms ms W W V V V V V V V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A
VOLTAGE REFERENCE
ELECTRICAL CHARACTERISTICS (VCC = 15.5 V, for typical values TA = 25C, for min/max values TJ = -25 to 125C)
Reference Undervoltage Lockout Threshold
Maximum Vref Output Current
Load Regulation (IOut = 0 mA to 5.0 mA)
Line Regulation (VCC = 10 V to 20 V)
Reference Output Voltage (IOut = 0 mA, TJ = 25C)
Characteristic
http://onsemi.com
MC33364
5 Symbol Regload Regline Vref Vth IO 4.90 Min - - - - 5.05 Typ 4.5 0.3 2.0 5 5.20 Max 50 50 - - Unit mA mV mV V V
MC33364
30 25 OUTPUT VOLTAGE (V) 20 15 10 5.0 0 -5.0 5.0 ms/DIV VCC = 14 V CL = 1000 pF TA = 25C t DLY, WATCHDOG TIME DELAY ( s) 500
450 VCC = 15 V 400
350
300 -55
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Figure 5. Drive Output Waveform
Figure 6. Watchdog Timer Delay versus Temperature
6.0 I CC, SUPPLY CURRENT (mA)
1000 R JA(t), THERMAL RESISTANCE JUNCTION-TO-AIR ( C/W) D Suffix 16 Pin SOIC
4.0 Circuit of Figure 12 TA = 25C 2.0
100
0 4.0
6.0
8.0
10
12
14
16
10 0.01
0.1
1.0 t, TIME (s)
10
100
VCC, SUPPLY VOLTAGE (V)
Figure 7. Supply Current versus Supply Voltage
Figure 8. Transient Thermal Resistance
40 FC-to-Vref CURRENT SENSE VOLTAGE 35 MINIMUM OFF-TIME (ms) 30 25 20 15 10 5 FC-to-Gnd 0 10 100 RESISTOR (kW) 1000
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 D Suffix 16 Pin SOIC TA = 25C VCC = 15 V
FEEDBACK VOLTAGE
Figure 9. Minimum Off-time versus Timing Resistor on the FC Pin
Figure 10. Feedback Voltage versus Current Sense Voltage
http://onsemi.com
6
MC33364
OPERATING DESCRIPTION
Introduction
The MC33364 series represents a variable-frequency current-mode critical-conduction solution with integrated high voltage startup and protection circuitry to implement an off-line flyback converter for modern consumer electronic power supplies. Different frequency clamp options offer different customized needs. This device series includes an integrated 700 V Very High-Voltage (VHV) start-up circuit. Thus, it is possible to design an application with universal input voltage from 85 Vac to 265 Vac without any additional startup circuits or components. The critical conduction feature offers some advantages. First, the MOSFET turns on at zero current and the diode turns off at zero current. The zero current reduces these turn-on and turn-off switching losses. It also reduces the Electro-Magnetic Interface (EMI) of the SMPS and a less expensive rectifier can be used. Second, by preventing the SMPS from entering the discontinuous conduction mode (DCM), the peak MOSFET drain current is limited to only twice the average input current. It needs a smaller and less expensive MOSFET. Third, by preventing the SMPS from entering the Continuous Conduction Mode (CCM), the flyback topology transfer function stays first-order and its feedback compensation network is considerably simplified. It also maximizes the power transfer by the flyback transformer to its 1/2 L I2 limits. A description of each of the functional blocks is given below. The representative block diagram and typical application circuit are in Figure 1 and Figure 2.
Line, VCC, Startup Circuit and Reference Voltage
The Line pin is capable of a maximum 700 V so that it is possible to connect this pin directly to the rectified high-voltage Alternating Current (AC) input for minimizing the number of external components. There is a startup circuit block that regulates voltage from the Line pin to the VCC pin in an abnormal situation. In normal conditions, the auxiliary winding powers up the VCC and this startup circuit is opened and saves approximate 0.7 W of power compared to the resistor bootstrapped circuits. In normal operation, the auxiliary winding powers up the VCC voltage. This voltage is a constant value between the UVLO limits (7.6 V and 15 V). It is further regulated to a constant 5 V reference voltage Vref for the internal circuitry usage. As long as the VCC voltage is between 7.6 V and 15 V, it means the auxiliary winding can provide voltage as in normal condition. The device recognizes that there is no fault in the circuit and the device remains in the normal operation status. However, when the auxiliary winding cannot power up VCC, the VCC voltage will reach its UVLO limit. The device recognizes that it is an abnormal situation (such as startup or output short-circuited). The VCC voltage is not constant in
this case. Figure 3 shows the timing diagram in a fault condition. There are three Under-Voltage Lock-Out (UVLO) thresholds with respect to VCC. The upper threshold is 15 V. When this limit is reached, the startup circuit block turns off and VCC declines due to power consumption of the circuitry. The startup circuit block turns on when VCC reaches 7.6 V and if Vref is higher than 3.7 V. It is the second threshold of VCC. If Vref is smaller than 3.7 V, the startup circuit will turn on when VCC reaches a temperature dependent value VT ranging between 3.5 V and 6 V. It is the last threshold of VCC. This temperature dependent threshold is lower when temperature is higher so that it takes a longer time to restore the VCC. It is a protection feature, which allows more dead time for cooling in high temperature condition. There is an UVLO in the Vref regulator block. When VCC falls below typical 8.1 V in abnormal situation, the Vref regulator block stops. Vref and VCC collapses due to power consumption of the circuitry. When Vref collapses to below 3.7 V, the device cannot provide the Drive output and makes a dead time. This dead time is designed for minimal power transfer in the abnormal conditions. The dead time ends when VCC reaches 15 V after reaching the UVLO limit VT (3.5 to 6 V). Reaching VT enables the startup circuit block, charging up the VCC capacitor again. When VCC reaches 15 V again, the Vref regulator block turns on and allows the output to work again. It is recommended to put a 0.1 uF capacitor on Vref pin for stability of the voltage buffer. The VCC capacitor is relatively larger than this 0.1 uF capacitor, making a longer VCC charging time from VT to 15 V and a longer dead time in the abnormal or fault conditions.
Zero Current Detect
To achieve critical conduction mode, MOSFET conduction is always initiated by sensing a zero current signal from the Zero Current Detect (ZCD) pin. The ZCD pin indirectly monitors the inductor current by sensing the auxiliary winding voltage. When the voltage falls below a threshold of 1.0V, the comparator resets the RS latch to turn the MOSFET on. There is 200 mV of hysteresis built into the comparator for noise immunity and to prevent false tripping. There are 10 V and 0.7 V clamps in the ZCD pin for protection. An external resistor is recommended to limit the input current to 2 mA to protect the clamps.
Watchdog Timer
A watchdog timer block is added to the device to start or restart the Drive output when something goes wrong in the ZCD. When the inductor current reaches zero for longer than approximate 410 ms, the timer reset the RS latch and that turns the MOSFET on.
http://onsemi.com
7
MC33364
Current Sense and Feedback Regulation Frequency Clamp Options
Current-mode control is implemented with the Current Sense (CS) pin and Feedback (FB) pin. The FB pin is internally pulled up with a 5 kOhm resistor from the 5 V Vref. There is a resistor divider circuit and a 0.1 V offset in this functional block. The following equation describes the relation between the voltages of the FB and CS pins, VFB and VCS respectively.
VCS(max) + VFB 4 * 0.1 V
When the output is short circuited, there is no feedback signal from the opto coupler and the FB pin is opened. It gives VFB = 5 V and the maximum voltage of the CS pin is 1.15 V. When the voltage exceeds 1.15 V, the current sense comparator turns on and terminates the MOSFET conduction. It stops current flowing through the sense resistor (RSense) and hence the sense resistor limits the maximum MOSFET drain current by the following equation.
Maximum Drain Current + 1.15 Rsense
The drawback of critical conduction mode is variable switching frequency. The switching frequency can increase dramatically to hundreds of kHz when the output current is too low or vanishes. It is a big problem when EMI above 150 kHz is concerned. Frequency Clamp (FC) is an optional feature in the device to limit the upper switching frequency to nominal 126 kHz by inserting a minimum off-time (toff(min)). When a minimum off-time is inserted, the maximum frequency (fmax) limit is set.
f max + 1 ton(min) ) toff(min)
When the output voltage is too high, the FB pin voltage is pulled down by the opto coupler current and the duty ratio is reduced. The output voltage is then regulated. There is a Leading Edge Blanking (LEB) circuit with 250 ns propagation delay to prevent false triggering due to parasitics in the CS pin. It makes a minimum on-time of the MOSFET (ton(min)).
Thermal Shutdown
There is a thermal shutdown block to prevent overheating condition and protect the device from overheating. When temperature is over 180_C, the Drive output and startup circuit block are disable. The device resumes operation when temperature falls below 130_C.
Gate Drive Output
The SMPS is forced to operate in DCM when the maximum frequency is reached. The minimum off-time is immediately counted after the driving signal goes low. If the ZCD signal comes within this minimum off-time, the ZCD information is ignored until the minimum off-time expires. The next ZCD signal starts the MOSFET conduction. There are three available FC options: MC33364D - adjustable minimum off-time by external resistor, MC33364D1 - 6.9 us fixed minimum off-time, and MC33364D2 - no minimum off-time (FC disable). The MC33364D has a FC pin, which can vary the minimum off-time (or the maximum frequency) externally in Figure 11. If the FC pin is opened, the minimum off-time is fixed at 6.9 us. If the FC pin is grounded, the clamp is disabled, and the SMPS will always operate in critical mode. It is generally not recommended to sink or source more than 80 uA from the FC pin because high currents may cause unstable operation.
Vref FC
The IC contains a CMOS output driver specifically designed for direct drive of power MOSFET. The Drive Output typical rise and fall times are 50 ns with a 1.0 nF load. Unbalanced Source and Sink eliminates the need for an external resistor between the device Drive output and the Gate of the external MOSFET. Additional internal circuitry has been added to keep the Drive Output in a sinking mode whenever the UVLO is active. This characteristic eliminates the need for an external gate pull-down resistor.
FC Increase toff
GND Decrease toff
FC
FC
GND toff = 6.9us toff = 0us (FC disable)
Figure 11. Frequency Clamp Setting
http://onsemi.com
8
MC33364
APPLICATION INFORMATION
Design Example
Design an off-line Flyback converter according to the following requirements: Output Power: 12 W Output: 6.0 V @ 2 Amperes Input voltage range: 90 Vac - 270 Vac, 50/60 Hz The operation for the circuit shown in Figure 12 is as follows: the rectifier bridge D1-D4 and the capacitor C1 convert the ac line voltage to dc. This voltage supplies the primary winding of the transformer T1 and the startup circuit in U1 through the line pin. The primary current loop is closed by the transformer's primary winding, the TMOS switch Q1 and the current sense resistor R7. The resistors R5, R6, diode D6 and capacitor C4 create a snubber clamping network that protects Q1 from spikes on the primary winding. The network consisting of capacitor C3, diode D5 and resistor R1 provides a VCC supply voltage for U1 from the auxiliary winding of the transformer. The resistor R1 makes VCC more stable and resistant to noise. The resistor R2 reduces the current flow through the internal clamping and protection zener diode of the Zero Crossing Detector (ZCD) within U1. C3 is the decoupling capacitor of the supply voltage. The resistor R3 can provide additional bias current for the optoisolator's transistor. The diode D8 and the capacitor C5 rectify and filter the output voltage. The TL431, a programmable voltage reference, drives the primary side of the optoisolator to provide isolated feedback to the MC33364. The resistor divider consisting of R10 and R11 program the voltage of the TL431. The resistor R9 and the capacitors C7 and C8 provide frequency compensation of the feedback loop. Resistor R8 provides a current limit for the opto coupler and the TL431. Since the critical conduction mode converter is a variable frequency system, the MC33364 has a built-in special block to reduce switching frequency in the no load condition. This block is named the "frequency clamp" block. MC33364 used in the design example has an internal frequency clamp set to 126 kHz. However, optional versions with a disabled or variable frequency clamp are available. The frequency clamp works as follows: the clamp controls the part of the switching cycle when the MOSFET switch is turned off. If this "off-time" (determined by the reset time of the transformer's core) is too short, then the frequency clamp does not allow the switch to turn-on again until the defined frequency clamp time is reached (i.e., the frequency clamp will insert a dead time). There are several advantages of the MC33364's startup circuit. The startup circuit includes a special high voltage switch that controls the path between the rectified line voltage and the VCC supply capacitor to charge that capacitor by a limited current when the power is applied to the input. After a few switching cycles the IC is supplied from the transformer's auxiliary winding. After VCC reaches the undervoltage lockout threshold value, the
startup switch is turned off by the undervoltage and the overvoltage control circuit. Because the power supply can be shorted on the output, causing the auxiliary voltage to be zero, the MC33364 will periodically start its startup block. This mode is named "hiccup mode". During this mode the temperature of the chip rises but remains protected by the thermal shutdown block. During the power supply's normal operation, the high voltage internal MOSFET is turned off, preventing wasted power, and thereby, allowing greater circuit efficiency. Since a bridge rectifier is used, the resulting minimum and maximum dc input voltages can be calculated:
V V in(min) dc + 2 xV in(min) ac + 2 (90 Vac) + 127 V 2 (270 Vac) + 382 V
in(max)
dc + 2 xV
in(max)
ac +
The maximum average input current is:
I in + P out nV in(min) + 12 W + 0.118 A 0.8(127 V)
where n = estimated circuit efficiency. A TMOS switch with 600 V avalanche breakdown voltage is used. The voltage on the switch's drain consists of the input voltage and the flyback voltage of the transformer's primary winding. There is a ringing on the rising edge's top of the flyback voltage due to the leakage inductance of the transformer. This ringing is clamped by the RCD network. Design this clamped wave for an amplitude of 50 V below the avalanche breakdown of the TMOS device. Add another 50 V to allow a safety margin for the MOSFET. Then a suitable value of the flyback voltage may be calculated:
V flbk *V * 100 V in(max) TMOS + 600 V * 382 V * 100 V + 118 V V +V + 127 V +V
Since this value is very close to the Vin(min), set:
flbk V in(min)
The Vflbk value of the duty cycle is given by:
max + V flbk flbk 127 V + + 0.5 [127 V ) 127 V] )V in(min)
The maximum input primary peak current:
I ppk + 2I in + 2.0(0.118 A) + 0.472 A max 0.5
Choose the desired minimum frequency fmin of operation to be 70 kHz. After reviewing the core sizing information provided by a core manufacturer, a EE core of size about 20 mm was chosen. Siemens' N67 magnetic material is used, which corresponds to a Philips 3C85 or TDK PC40 material.
http://onsemi.com
9
MC33364
The primary inductance value is given by:
max V Lp + I ppk in(min) f min + 0.5(127 V) + 1.92 mH (0.472 A)(70 kHz)
The approximate value of rectifier capacitance needed is:
t (I ) (5 m sec)(0.118 A) C1 + off in + + 11.8 mF V 50 V ripple
The manufacturer recommends for that magnetic core a maximum operating flux density of:
B max + 0.2 T
The cross-sectional area Ac of the EF20 core is:
A c + 33.5 mm 2
The operating flux density is given by:
B max + L pI ppk N pA c
where the minimum ripple frequency is 2 times the 50 Hz line frequency and toff, the discharge time of C1 during the haversine cycle, is assumed to be half the cycle period. Because we have a variable frequency system, all the calculations for the value of the output filter capacitors will be done at the lowest frequency, since the ripple voltage will be greatest at this frequency. When selecting the output capacitor select a capacitor with low ESR to minimize ripple from the current ripple. The approximate equation for the output capacitance value is given by:
C5 + I out (f )(V ) min rip + 2A + 286 mF (70 kHz)(0.1 V)
From this equation the number of turns of the primary winding can be derived:
np + ppk B maxA c 2 L pI
The AL factor is determined by:
A+ + L n 2p Lp L p B maxA c 2 Lp I ppk 2 2 + 105 nH
Determining the value of the current sense resistor (R7), one uses the peak current in the predesign consideration. Since within the IC there is a limitation of the voltage for the current sensing, which is set to 1.2 V, the design of the current sense resistor is simply given by:
R7 + V cs + 1.2 V + 2.54 W [ 2.2 W I 0.472 A ppk
+
0.2 T 33.5 E-6 m 2 .00192 H (0.472 A)
From the manufacturer`s catalogue recommendation the core with an AL of 100 nH is selected. The desired number of turns of the primary winding is:
np + Lp A L 12 (0.00192 H) + (100 nH) 12 + 139 turns
The error amplifier function is provided by a TL431 on the secondary, connected to the primary side via an optoisolator, the MOC8102. The voltage of the optoisolator collector node sets the peak current flowing through the power switch during each cycle. This pin will be connected to the feedback pin of the MC33364, which will directly set the peak current. Starting on the secondary side of the power supply, assign the sense current through the voltage-sensing resistor divider to be approximately 0.25 mA. One can immediately calculate the value of the lower and upper resistor:
R V (TL431) + R11 + ref + 2.5 V + 10 k lower I 0.25 mA div V out * V I (TL431) ref
The number of turns needed by the 6.0 V secondary is (assuming a Schottky rectifier is used):
ns + Vs ) V fwd 1- max n p in(min) + 7 turns
R upper + R10 +
max V +
div
6.0 V ) 0.3 V 1 * 0.5 139 0.5 127 V
+ 6.0 V * 2.5V + 14 k 0.25 mA
The auxiliary winding to power the control IC is 16 V and its number of turns is given by:
naux + (V aux ) V )(1 * max)n p fwd in(min) )
The value of the resistor that would provide the bias current through the optoisolator and the TL431 is set by the minimum operating current requirements of the TL431. This current is minimum 1.0 mA. Assign the maximum current through the branch to be 5 mA. That makes the bias resistor value equal to:
R bias +R + S + V out * [V (TL431) ) V ] LED ref I LED
max(V +
(16 V ) 0.9 V)(1 * 0.5)139 + 19 turns [0.5(127 V)]
6.0 V * [2.5V ) 1.4V] + 420 W [ 430 W 5.0 mA
http://onsemi.com
10
MC33364
The MOC8102 has a typical current transfer ratio (CTR) of 100% with 25% tolerance. When the TL431 is full-on, 5 mA will be drawn from the transistor within the MOC8102. The transistor should be in saturated state at that time, so its collector resistor must be
R V * V sat + ref + 5.0 V * 0.3 V + 940 W collector I 5.0 mA LED
The gain exhibited by the open loop power supply at the high input voltage will be:
V A+ in max in max * V out 2 Ns + 2 (382 V * 6.0 V) (7) (382 V)(1.2 V)(139)
(V
)(V error)(Np)
+ 15.53 + 23.82 dB
Since a resistor of 5.0 k is internally connected from the reference voltage to the feedback pin of the MC33364, the external resistor can have a higher value
R ext + R3 + )(R ) int collector + (5.0 k)(940) (R ) * (R ) 5.0 k * 940 int collector + 1157 W [ 1200 W (R
The maximum approximately:
recommended
bandwidth
is
f c + fs min + 70 kHz + 14 kHz 5 5
The gain needed by the error amplifier to achieve this bandwidth is calculated at the rated load because that yields the bandwidth condition, which is:
Gc + 20 log fc f ph * A + 20 log 14 kHz * 23.82 dB 177 + 14.14 dB
This completes the design of the voltage feedback circuit. In no load condition there is only a current flowing through the optoisolator diode and the voltage sense divider on the secondary side. The load at that condition is given by:
R noload + + V out (I LED )I )
The gain in absolute terms is:
A c + 10 (Gc 20) + 10 (14.14 20) + 5.1
div
6.0 V + 1143 W (5.0 mA ) 0.25 mA)
Now the compensation circuit elements can be calculated. The output resistance of the voltage sense divider is given by the parallel combination of resistors in the divider:
R in + R upper || R lower + 10 k || 14 k + 5833 W R9 + (Ac) (R ) + 29.75 k [ 30 k in C8 + 1 2p (A c) (R ) (f c) in + 382 pF [ 390 pF
The output filter pole at no load is:
f ph 1 C ) noload out 1 + + 0.46 Hz (2p)(1143)(300 mF) + ( 2p R
In heavy load condition the ILED and Idiv is negligible. The heavy load resistance is given by:
R heavy V + out + 6.0 V + 3.0 W I out 2.0 A
The compensation zero must be placed at or below the light load filter pole:
C7 + 1 2p (R9) (f pn) + 11.63 mF [ 10 mF
The output filter pole at heavy load of this output is
f ph + (2p R 1 1 + + 177 Hz (2p)(3)(300 mF) C) heavy out
http://onsemi.com
11
MC33364
1N4006 D1 85 to 265 VAC EMI Filter D2 D3 D4 T1 D8 MBR340 C5 300mF R5 47 K R6 47 K C4 1mF 6.0 V 2.0 A + C1 10mF 400V
D5 1N4934 R1 56
Line Vcc Vcc UVLO Reference 15 / 7.6 Vref Buffer ZCD ZCD 4.7 Restart Delay Ref UVLO StartUp
C3 20mF
D6 MUR160
R2 22 k
VREF
10V
1.2/1.0
Watchdog Timer R R S
MC33364D
Vcc GATE Q
C10 0.1mF
R3
FB
5k Current Sense 1.25V 45k 15k 0.1V 2V
Q1 MTD1N60 R4 470 (optional) R7 2.2
Frequency clamp
Thermal shutdown
PGND
R8 430 R10 14 k 5 4 R9 39 k 1 2 C7 10 mF C8 330 pF R11 10 k
LEB 4k FC 10V AGND
CS
U3 MOC8102
U2 TL431
3
1 2
Figure 12. Circuit in the Design Example
http://onsemi.com
12
MC33364
The described critical conduction mode flyback converter has the following performance and maximum ratings: Output power 12W Output 12V @ 1Amp max Input voltage range 90VAC - 270VAC J1 3 1 Line J2 1 Gnd 2 D1 S380 T1 10uF 400V C4 10uF 220 2 1 R1 D2 1N4148 R2 100k 8 7 U1 LINE VCC ZCD 1 R4 47k 9 7 R3 47k C5 1nF 2 D3 MURS160T3 4 6 2 R5 2.2 5 4 2 U3 MOC8102 1 3 Q1 MTD1N60 C9 100nF 3 1 U2 1 TL431 2 R9 4k7 J4 1 -Vout D4 4 MBRD360 C6 300uF R6 2k7 R7 820 R8 18k J3 1 +Vout
5
GATE MC33364 GND CS VREF FB 0.1uF 3
4
Figure 13. Critical Conduction Mode Flyback Converter CONVERTER TEST DATA
Test Line Regulation Load Conditions Vin = 120VAC to 240VAC, Iout = 0.8A Vin = 120VAC, Iout = 0.2A to 0.8A Vin = 240VAC, Iout = 0.2A to 0.8A Output Ripple Vin = 120VAC, Iout = 0.8A Vin = 240VAC, Iout = 0.8A Efficiency Vin = 120VAC, Iout = 0.8A Vin = 240VAC, Iout = 0.8A Power Factor Vin = 120VAC, Iout = 0.8A Vin = 240VAC, Iout = 0.8A DV = 50mV DV = 40mV DV = 40mV DV = 290mV DV = 24mV h = 78.0% h = 79.4% Pf = 0.491 Pf = 0.505 Results
Vout
Vout
Iout
Iout
Ch1: 2.0V/div Ch2: 200mA/div
2.0 msec/div
Ch1: 2.0V/div Ch2: 200mV/div
2.0 msec/div
Figure 14. Load Regulation 120V
Figure 15. Load Regulation 240V
http://onsemi.com
13
MC33364
J2 1 2 Output 12 V @ 0.8 Amp max Input Voltage Range 90 - 270 Vac, 50/60 Hz
R13 22 k
R12 82 k
R11 10 k
5 VS 6 CSB
GND 4 R10 0.25 R9 100
5.1 V R8 4.7 k D8 B2X84C5V1LT1 C5 100 mF C6 1.0 mF R7 100 9 T1 5 4 7
CMP 3 U2 7 VCC MC33341 CTA 2 CSA 1 8 DO
C7 33 nF
D7 1N4148
D6 MURS320T3 2 1
3 C4 1.0 nF
2 D5 MURS 160T3 Q1 MTD1N60E R4 2.2 5 4
R6 47 k
R5 47 k
U3 MOC8102
D3 1N4148 R1 220 C2 20 mF R3 22 k 6 Gate 1 ZCD 7 VCC C1 D1 B250R F1 T 0.2 A 8 Line 10 mF 400 V 2 CS U1 MC33364D1 GND 5 FB 3 C3 Vref 4 0.1 mF
12 J1 Line
T1 = 139 Turns #28 Awg, primary winding 2 - 3 7 Turns, Bifilar 2 x #26 Awg, output winding 9 - 7 19 Turns #28 Awg, auxiliary winding 4 - 5 on Philips EF20-3C85 core gap for a primary inductor of 1.92 mH.
Figure 16. Universal Input Battery Charger
http://onsemi.com
14
MC33364
PACKAGE DIMENSIONS
SO-8 D1, D2 SUFFIX PLASTIC PACKAGE CASE 751-07 ISSUE AH
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
MC33364
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751K-01 ISSUE O
-A-
16 9
0.25 (0.010)
-B-
P
M_ F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.368 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
1
8
G R X 45 _ C -T- K
14 X D SEATING PLANE
M
B
S
J
M
0.25 (0.010)
TA
S
B
S
The product described herein (MC33364), may be covered by one or more of the following U.S. patents: 5,418,410; 5,862,045; 5,973,528. There may be other patents pending. GreenLine is a trademark of Motorola, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
16
MC33364/D

▲Up To Search▲

Price & Availability of MC3336406

	To Download MC3336406 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .